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APL hardware: Difference between revisions
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The MLIM is a 32x32 array of memory cells. Each memory cell contains four shift registers named A, B, C, and T. This is equivalent to creating 4 arrays of memory cells with one shift register each. The arrays created by registers A, B, and C are used to store and operate on data, while T is temporary array storage for the result of an operation. The operations which the MLIM can perform can either read from A and B to store the result in C, or read from C and B and store the result in A. The RL processing helps place each memory array in the correct locations of A, B, and C such that the operands line up before the MLIM performs its operations. | The MLIM is a 32x32 array of memory cells. Each memory cell contains four shift registers named A, B, C, and T. This is equivalent to creating 4 arrays of memory cells with one shift register each. The arrays created by registers A, B, and C are used to store and operate on data, while T is temporary array storage for the result of an operation. The operations which the MLIM can perform can either read from A and B to store the result in C, or read from C and B and store the result in A. The RL processing helps place each memory array in the correct locations of A, B, and C such that the operands line up before the MLIM performs its operations. | ||
MA1 through MA16 are each 32x32 arrays of memory cells which can each store one word (16 bits). This means the total array storage of the computer is 16,384 words. | MA1 through MA16 are each 32x32 arrays of memory cells which can each store one word (16 bits). This means the total array storage of the computer is 16,384 words. | ||
The IMU is a temporary location for instructions, to "give the programmer a usable memory of 16,384 words." Each cell is a 32-bit read-only memory cell. | The IMU is a temporary location for instructions, to "give the programmer a usable memory of 16,384 words." Each cell is a 32-bit read-only memory cell. | ||
The RL is a specialized transfer system that can perform row- or column-wise transfer of data to the MLIM or VAs. It can also index into matrices and vectors during transfer. | The RL is a specialized transfer system that can perform row- or column-wise transfer of data to the MLIM or VAs. It can also index into matrices and vectors during transfer. | ||
The IOC is a generalized input/output system that can be modified for any purpose. Input from the IOC is fed through the PP before it is fed into the RL. | The IOC is a generalized input/output system that can be modified for any purpose. Input from the IOC is fed through the PP before it is fed into the RL. | ||
The PP would handle storage allocation, basic operations, and other operations which the MLIM cannot perform. | The PP would handle storage allocation, basic operations, and other operations which the MLIM cannot perform. | ||
VA1 through VA32 are each composed of two 32 bit registers A and B. Register A of each accumulator is connected to the Routing and Control Logic board via a decoder. Each decoder is connected to its VA via a 32-bit bus, to the Routing and Control Logic board via a 32-bit output bus, and to the PP via a 5-bit input logic bus. if p is the value on the 5-bit bus such that 0≤p≤31, then the 32-bit bus shifts the bits in the output such that it returns 32-p, 32-p+1, ..., 32. Thus, it shifts the input left by p bits, masking out the indices that are greater than or equal to 32. Thus, this type of register is called a ''shift register''. The decoders are considered a part of the RL cell. Register B is directly connected to register A, and has a direct vector routing bus connected to the Routing and Control Logic board. | VA1 through VA32 are each composed of two 32 bit registers A and B. Register A of each accumulator is connected to the Routing and Control Logic board via a decoder. Each decoder is connected to its VA via a 32-bit bus, to the Routing and Control Logic board via a 32-bit output bus, and to the PP via a 5-bit input logic bus. if p is the value on the 5-bit bus such that 0≤p≤31, then the 32-bit bus shifts the bits in the output such that it returns 32-p, 32-p+1, ..., 32. Thus, it shifts the input left by p bits, masking out the indices that are greater than or equal to 32. Thus, this type of register is called a ''shift register''. The decoders are considered a part of the RL cell. Register B is directly connected to register A, and has a direct vector routing bus connected to the Routing and Control Logic board. | ||
It is an important functionality that vectors can be loaded into right justified into a VA, then read offset such that its length ≤ 32. Because of register B, each accumulator can perform reductions by repeatedly adding the register A. | |||
It is an important functionality that vectors can be loaded into right justified into a VA, then read offset such that its length ≤ 32. Because of register B, each accumulator can perform reductions by repeatedly adding the register A. | |||
=== Supported Operations === | === Supported Operations === | ||