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APL hardware: Difference between revisions
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* a preprocessor (PP) | * a preprocessor (PP) | ||
The MLIM is a 32x32 array of memory cells. Each memory cell contains four shift registers named A, B, C, and T. This is equivalent to creating 4 arrays of memory cells with one shift register each. The arrays created by registers A, B, and C are used to store and operate on data, while T is temporary array storage for the result of an operation. The operations which the MLIM can perform can either read from A and B to store the result in C, or read from C and B and store the result in A. The RL processing | The MLIM is a 32x32 array of memory cells. Each memory cell contains four shift registers named A, B, C, and T. This is equivalent to creating 4 arrays of memory cells with one shift register each. The arrays created by registers A, B, and C are used to store and operate on data, while T is temporary array storage for the result of an operation. The operations which the MLIM can perform can either read from A and B to store the result in C, or read from C and B and store the result in A. The RL processing helps place each memory array in the correct locations of A, B, and C such that the operands line up before the MLIM performs its operations. | ||
MA1 through MA16 are each 32x32 arrays of memory cells which can each store one word (16 bits). This means the total array storage of the computer is 16,384 words. | MA1 through MA16 are each 32x32 arrays of memory cells which can each store one word (16 bits). This means the total array storage of the computer is 16,384 words. | ||
The IMU is a temporary location for instructions, to "give the programmer a usable memory of 16,384 words." Each cell is a 32-bit read-only memory cell. | The IMU is a temporary location for instructions, to "give the programmer a usable memory of 16,384 words." Each cell is a 32-bit read-only memory cell. | ||